A Pipelined Multi-core Mips Machine Hardware Implementation And Correctness Proo - Mikhail Kovalev - Paperback - en Book

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A Pipelined Multi-core Mips Machine Hardware Implementation And Correctness Proo - Mikhail Kovalev - Paperback - en Book

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A Pipelined Multi-core Mips Machine Hardware Implementation And Correctness Proo - Mikhail Kovalev - Paperback - en Book

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A Pipelined Multi-core Mips Machine Hardware Implementation And Correctness Proo - Mikhail Kovalev - Paperback - en Book

This Monograph Is Based On The Third Author's Lectures On Computer Architecture, Given In The Summer Semester 2013 At Saarland University, Germany. It Contains A Gate Level Construction Of A Multi-core Machine With Pipelined Mips Processor Cores And A Sequentially Consistent Shared Memory.the Book Contains The First Correctness Proofs For Both The Gate Level Implementation Of A Multi-core Processor And Also Of A Cache Based Sequentially Consistent Shared Memory. This Opens The Way To The Formal Verification Of Synthesizable Hardware For Multi-core Processors In The Future.constructions Are In A Gate Level Hardware Model And Thus Deterministic.
  • 品牌: Unbranded
  • 类别: 计算机与互联网
  • 语言: en
  • 作者: Mikhail Kovalev
  • 长度: 364
  • 出版社／标签: Springer Nature B.V
  • 格式: Paperback
  • Fruugo ID: 490582810-1013632908
  • ISBN: 9783319139050

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